Now using hierarchical designing it is very easy to write Verilog code of 4×2 mux by just instantiating three 2×1 muxes. This combination is shown below: S0įocus on the diagram of 2×1 mux and you will get it how this 4×2 mux works. When S1 is set to HIGH it will select i1 and i3 now if s0 is LOW output will have i1 otherwise i3 and similar for i0 and i2. Now we have constructed our 2×1 mux we can easily construct 4×2 mux using three of these 2×1 muxes as shown in the block diagram given below: In a hierarchical design, all we need is to design a small block and construct a big block using these small blocks. We can easily write its Verilog code given below: Truth table for 2×1 mux is given below: Inputįrom above table, we can deduce its boolean expression which is simply: \(\text = AS BS’\) As (A AND 1 = A) and due to the presence of NOT gate B data will have no effect on output. You can select a data line by setting a switch to 0 or 1 as shown in the diagram below:įrom the above figure, we can observe that if we set a switch to 1 then out will have data line A. This example problem will focus on how you can construct 4×2 multiplexer using 2×1 multiplexer in Verilog.Ī multiplexer is a device that can transmit several digital signals on one line by selecting certain switches.įor example, in a 2×1 multiplexer, there is one select switch and two data lines. #4 to 16 decoder using 2 to 4 decoder verilog code full
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